AST-E-Beam Evaporator,Magnetic Enhanced Sputtering,Magnetic Enhanced Sputter,advanced packaging

Wire Bonding as a traditional packaging technique for interconnecting chips and substrates fails to meet the compact, petite, light-weight and slender requirements for portable and high performance microelectronics product applications. Flip Chip Bonding technique uses bumps instead of gold wire has become a replacement technique and has been the key core technology in wafer level packaging. Today, Flip Chip Bonding technique has been widely applies on the following products:

1. High-end computer equipments with high performance, high I/O density and high heat sink requirements
2. Communication products with high I/O throughput and rigid signal transmission quality requirements
3. Portable consumer products with high integration requirements
4.Automobile parts with harsh temperature, humidity, vibration and anti-electromagnetic interference requirements
5.Low capacity, lightweight LCD driver IC Products.

Flip Chip Bonding technique is the process of making metal bumps on top of the chip I/O pad As the interconnecting media with the substrate. Based on wiring technique considerations, existing design is to place I/O pads Surrounding the chip. With the advancement of flip chip bonding and substrate production capability, I/O pads must be redistributed in an area array format to elevate assembly yield by increasing the inter-pad distance, this is called Redistribution.

There are two types of Redistribution:
1. Redistribution before the placement of IC protection layer: this can be viewed as part of the IC fabrication process with an additional metal layer. This can be perform within the IC plant for easier quality control but with higher cost.
2. Redistribution after the placement of IC protection layer: process with similar equipment level; can be manufactured by the bump foundry with lower cost.
(1) Deposit the first photosensitive electro-static materials on the wafer. (BCB or PI)
(2) Open windows in BCB/PI over the wire bond pads using RIE photolithography
(3) Magnetic Enhanced Sputtering and patterning to define the traces and bump locations. (Al/Ni/Cu/Ti or Al)
(4) Etching required metal wiring traces
(5) Repeat Steps (1)~(4)

After pad redistribution, bumps need to produced on top of the pad to be the interconnection media with the substrate.?Bump materials varies based on the application, but mainly Sn/Pb solder and Au.?For future environmental protection concerns, lead-free bumps will replace existing Sn/Pb materials such as Sn-3.5%Ag, Sn-0.7%Cu and Sn-3.5%Ag-0.7%Cu series.

Major bump manufacturing processes include:
1. Under Bump Metallization (UBM): provides interconnection and excellent diffusion barrier between metal pads and bumps, mainly includes adhesion layer, diffusion barrier layer and solder wettable layer. Generic UBM systems includes Cr/Cr/Cu/Cu, Ti(w)/Cu/Ni, Al/NiV/Cu and electroless Ni/Au...etc. Manufacturing technique include E-Beam Evaporator, Magnetic Enhanced Sputter and Electroless Ni/Au methods.
2. Bump:
(1) Sn/Pb Bump IBM C4 E-Beam Evaporator manufacturing Process (Premium Quality with higher cost):
(A) Mo mask production
(B) UBM E-Beam Evaporator(Cr/CrCu/Cu)
(C) Sn/Pb Bump E-Beam Evaporator
(D) Reflow

(2) Sn/Pb bump electroplating process (High quality with lower cost inc comparison with C4)
(A) UBM Magnetic Enhanced Sputter(Ti(w)/Cu/Ni)
(B) Photoresist application
(C) UBM and bump electroplating
(D) Stripping
(E) UBM etching
(F) Reflow

(3) Sn/Pb bump printing process (low cost):
(A) UBM Magnetic Enhanced Sputter(Al/NiV/Cu)
(B) Photoresist application
(C) UBM etching
(D) Bump printing
(E) Reflow

((4) Au bump electroplating process (for LCD and consumer device application):
(A) UBM Magnetic Enhanced Sputte(Ni/Au)
(B) Photoresist coating and develop
(C) Gold bumping electroplating
(D) Stripping
(E) UBM Etching
(F) Annealing

Advanced wafer level packaging technique is getting matured with the development of the Flip Chip Bonding technique. Current research & development focus has concentrated on the following three main issues:
(1) following the industrial shift from 8-inch to 12-inc wafer
(2) shifting to lead-free solder (Sn/Ag) as the prefer material for wafer bumps and related wafer UBM lead-free printing technique
(3) research and development of new electro-sensitive dielectric materials to lower curing temperature to under 200 ℃ in comparison with the 500℃ for electro-sensitive BCB process and >350℃ for PI.